12月7日：Sri Parameswaran
发布时间：2018-12-06 浏览量：2081
报告题目： Minimally Biased Approximate Arithmetic Multipliers and Dividers
报告人： Prof.Sri Parameswaran University of New South Wales
主持人： 林学民 教授
报告时间：12月7日 周五15:30-17:00
报告地点： 中北校区数学馆东201
报告摘要：
Approximation has allowed humans to calculate fast with sufficient accuracy to execute tasks. Our hearing, seeing mechanisms are all examples of approximate mechanisms which serve us eminently well. In the domain of mathematics, there are numerous examples of approximation such as rounding, or Newton-Raphson Method to obtain values for integration and so on. In computing too, there are multiple instances such as MP3 encoding of music which removes what are unnecessary components from audio files so that the audio file can be made smaller.
In this talk we show a hardware method to reduce the size of integer and floating-point multipliers and dividers. Unfortunately, when arithmetic units are approximated, they tend to have a bias. Bias in error means that the average error tends to be either positive or negative, and the use of multiple units in a system will be disposed to accumulate these errors making the overall system impractical. Thus, it is necessary to have an approximate unit which is minimally biased. I will present a novel design method and circuits and systems which are small, extremely energy efficient and with little bias. I will also showcase some applications in which approximation makes little or no difference to the output yet saves much area and energy. We may even be able to limit our reliance on fixed point arithmetic!
Approximation has allowed humans to calculate fast with sufficient accuracy to execute tasks. Our hearing, seeing mechanisms are all examples of approximate mechanisms which serve us eminently well. In the domain of mathematics, there are numerous examples of approximation such as rounding, or Newton-Raphson Method to obtain values for integration and so on. In computing too, there are multiple instances such as MP3 encoding of music which removes what are unnecessary components from audio files so that the audio file can be made smaller.
In this talk we show a hardware method to reduce the size of integer and floating-point multipliers and dividers. Unfortunately, when arithmetic units are approximated, they tend to have a bias. Bias in error means that the average error tends to be either positive or negative, and the use of multiple units in a system will be disposed to accumulate these errors making the overall system impractical. Thus, it is necessary to have an approximate unit which is minimally biased. I will present a novel design method and circuits and systems which are small, extremely energy efficient and with little bias. I will also showcase some applications in which approximation makes little or no difference to the output yet saves much area and energy. We may even be able to limit our reliance on fixed point arithmetic!
报告人简介：
Sri Parameswaran is a Professor in the School of Computer Science and Engineering at the University of New South Wales. He also serves as the Postgraduate Research and Scholarships coordinator at the same school. Prof. Parameswaran received his B. Eng. Degree from Monash University and his Ph.D. from the University of Queensland in Australia. He has held visiting appointments at University of California, Kyushu University and Australian National University. He has also worked as a consultant to the NEC Research laboratories at Princeton, USA and to the Asian Development Bank in Philippines. His research interests are in System Level Synthesis, Low power systems, High Level Systems, Network on Chips and Secure and Reliable Processor Architectures. He is the Editor-in-Chief of IEEE Embedded systems Letters. He serves or has served on the editorial boards of IEEE Transactions on Computer Aided Design, ACM Transactions on Embedded Computing Systems, the EURASIP Journal on Embedded Systems and the Design Automation of Embedded Systems. He has served on the Program Committees of Design Automation Conference (DAC), Design and Test in Europe (DATE), the International Conference on Computer Aided Design (ICCAD), the International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS), and the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES).
Sri Parameswaran is a Professor in the School of Computer Science and Engineering at the University of New South Wales. He also serves as the Postgraduate Research and Scholarships coordinator at the same school. Prof. Parameswaran received his B. Eng. Degree from Monash University and his Ph.D. from the University of Queensland in Australia. He has held visiting appointments at University of California, Kyushu University and Australian National University. He has also worked as a consultant to the NEC Research laboratories at Princeton, USA and to the Asian Development Bank in Philippines. His research interests are in System Level Synthesis, Low power systems, High Level Systems, Network on Chips and Secure and Reliable Processor Architectures. He is the Editor-in-Chief of IEEE Embedded systems Letters. He serves or has served on the editorial boards of IEEE Transactions on Computer Aided Design, ACM Transactions on Embedded Computing Systems, the EURASIP Journal on Embedded Systems and the Design Automation of Embedded Systems. He has served on the Program Committees of Design Automation Conference (DAC), Design and Test in Europe (DATE), the International Conference on Computer Aided Design (ICCAD), the International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS), and the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES).
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